System and methods for dynamic pixel management of a cross pixel interconnected cmos image sensor

ABSTRACT

A camera using a CMOS image sensor based on a shared pixel array technology avails both high definition (HD) and ultra-high definition (UHD) resolution mode formats. Dynamic pixel management allows for both sequential and binned timing formats of pixel signals using switched capacitor noise reduction techniques. When UHD resolution mode is selected, noise can be reduced using both digital double sampling (DDS) or differential digital double sampling (dDDS), and when HD resolution mode is selected noise can be reduced using DDS. Additionally, both rolling shutter and global shutter modes can be selected when HD resolution mode is selected.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/697,349, filed Sep. 6, 2017, which claims priority to U.S.Provisional Application Ser. No. 62/385,204, filed on Sep. 8, 2016. U.S.application Ser. No. 15/697,349 is also a continuation-in-part of U.S.application Ser. No. 15/362,023, filed Nov. 28, 2016, which claimspriority to U.S. Provisional Application Ser. No. 62/385,027, filed onSep. 8, 2016. The entire contents of each of these applications ishereby incorporated by reference herein in their entirety.

TECHNICAL FIELD

The disclosure herein generally relates to digital cameras, and moreparticularly to cameras using complementary metal oxide semiconductor(CMOS) image sensors.

BACKGROUND

Complementary metal oxide semiconductor (“CMOS”) image sensors arewidely used in digital cameras to produce digital images by convertingoptical signals into electrical signals. In operation, CMOS imagesensors may convert an optical signal into an electrical signal using amultitude of pixels that each include a photodiode and a read-outcircuit. The photodiode generates electric charges using absorbed light,converts the generated electric charges into an analog current, anddelivers the analog current to the read-out circuit. The read-outcircuit may convert the analog signal into a digital signal and outputsthe digital signal.

Certain CMOS image sensor pixel circuits are formed using fourtransistors and are known and referred to as 4T image sensor pixels or“4T pixels.” FIG. 1 illustrates an exemplary design of a 4T pixel 110connected to a bit-line 120. As shown, the 4T CMOS image sensor pixel110 includes a photodiode (“PD”) that provides the photon to electronconversion, while a floating diffusion (“FD”) point provides theelectron to voltage conversion. The voltage per electron conversion ofthe FD is known as conversion gain (“CG”) and is an important parameterfor CMOS image sensors. Conversion gain boosts the pixel signal relativeto the analog noise, thereby reducing the noise floor, and therebyenabling performance at lower light levels.

For such CMOS image sensors, during the analog-to-digital conversionprocess, a comparator receives an analog voltage and compares the analogvoltage with a ramp voltage. In one implementation of a CMOS imagesensor, the comparator compares the analog voltage with the rampvoltage, and uses a counter to count until the ramp voltage is greaterthan an analog voltage. Once the counter stops counting, a count valueis digital data corresponding to an analog voltage, that is, the countvalue is the digital data into which the analog voltage has beenconverted.

Referring to FIG. 1, the pixel is reset when the reset transistor(“RST”) and transfer gate (“TG”) are turned on simultaneously, settingboth the floating diffusion FD and the photodiode PD to the VDD voltagelevel. Next, the transfer gate TG is turned off (disconnecting thephotodiode PD and floating diffusion FD) and the photodiode PD is leftto integrate light.

After integration, the signal measurement occurs. First, the resettransistor RST is turned on and off to reset the floating diffusion FD.Immediately after this, the reset level is sampled from the floatingdiffusion FD and stored on the column circuit, i.e., bit-line 120. Next,the transfer gate TG is turned on and off which allows charge on thephotodiode PD to transfer to the floating diffusion (FD). Once thecharge transfer is complete, this charge (the photodiode signal levelplus the floating diffusion reset level) is measured and stored onbit-line 120 as well.

These two stored voltages are then differenced (D_(sig)−D_(rst)) todetermine the photodiode signal level. The 4T pixel design 110significantly improves the performance of other CMOS image sensors,reducing both read noise and image lag. In addition, the design reducespixel source follower offsets and the like.

SUMMARY

In one exemplary aspect, an image sensing system is disclosed forproviding dynamic pixel management to switch operational modes betweenhigh definition (HD) and ultra-high definition. In this aspect, theimage sensor includes a complementary metal oxide semiconductor (CMOS)image sensor including a shared pixel array having a plurality of sharedpixel units that each comprises at least two photodiodes and a sharedfloating diffusion; a plurality of vertical and horizontal chargecircuitry coupled to the CMOS image sensor and configured to activatethe plurality of shared pixel units during image capture based on a setoperational mode of the image sensor; and a dynamic pixel managerconfigured to switch the operational mode of the CMOS image sensorbetween a UHD mode and a HD mode in response to a user selection of animage resolution for the image captured by the image sensor. Moreover,the image sensing system includes a UHD mode controller configured tocontrol the plurality of vertical and horizontal charge circuitry tosequentially transfer charge between the at least two photodiodes andthe shared floating diffusion of each shared pixel unit when the dynamicpixel manager sets the operational mode of the CMOS image sensor to theUHD mode to individually sample output values of each of the at leasttwo photodiode during the image capture by the image sensor; a HD modecontroller configured to control the plurality of vertical andhorizontal charge circuitry to bin charge concurrently between the atleast two photodiodes and the shared floating diffusion of each sharedpixel unit when the dynamic pixel manager sets the operational mode ofthe CMOS image sensor to the HD mode to collectively sample outputvalues of each shared pixel unit that combines output values of the atleast two photodiodes during the image capture by the image sensor; acolumn readout circuit having a plurality of storage capacitorsselectively coupled to the shared pixel array that are each configuredto store sampled output values of the at least two photodiode of eachshared pixel unit during the image capture in the UHD mode and to storesampled output values of each shared pixel unit during the image capturein the HD mode; and an image generating unit configured to generateimage data based on the stored sampled output values in the plurality ofstorage capacitors, the generated image configured to be displayed on adisplay device.

In another exemplary embodiment, a camera is disclosed for providingdynamic pixel management to switch operational modes between highdefinition (HD) and ultra-high definition. In this aspect, the cameraincludes an image sensor including a shared pixel array having aplurality of shared pixels that each comprises at least two photodiodesand a shared floating diffusion; a dynamic pixel manager configured toswitch an operational mode of the image sensor between a UHD mode and aHD mode based on a selected image resolution for an image capture by theimage sensor; a UHD mode controller configured to control the imagesensor to sequentially transfer charge between the at least twophotodiodes and the shared floating diffusion of each shared pixel whenthe dynamic pixel manager sets the operational mode of the image sensorto the UHD mode to individually sample photodiode output values of eachof the at least two photodiode during the image capture by the imagesensor; a HD mode controller configured to control the image sensor tobin charge concurrently between the at least two photodiodes and theshared floating diffusion of each shared pixel when the dynamic pixelmanager sets the operational mode of the image sensor to the HD mode tocollectively sample pixel output values of each shared pixel thatcombines output values of the at least two photodiodes during the imagecapture by the image sensor; and an image generating unit configured togenerate image data based on at least one of the individually sampledphotodiode output values during the UDH mode and the collectivelysampled pixel output values during the HD mode.

In another aspect, a camera is disclosed for providing dynamic pixelmanagement to switch operational modes between high definition (HD) andultra-high definition. In this aspect, the camera includes a camera modecontroller configured to switch the camera between a UHD mode and a HDmode based on a selected image resolution for an image capture; and animage sensor configured to individually sample sub-pixels of each pixelin an image sensor when the camera mode controller sets the camera tothe UHD mode for the image capture and to collectively sample thesub-pixels of each pixel in the image sensor when the camera modecontroller sets the camera to the HD mode for the image capture.

Other aspects of apparatuses described herein will become readilyapparent to those skilled in the art based on the following detaileddescription, wherein various aspects of memory are shown and describedby way of illustration. These aspects may be implemented in manydifferent forms and its details may be modified in various ways withoutdeviating from the scope of the present invention. Accordingly, thedrawings and detailed description provided herein are to be regarded asillustrative in nature and not as restricting the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated into and constitute apart of this specification, illustrate one or more example aspects ofthe present disclosure and, together with the detailed description,serve to explain their principles and implementations.

FIG. 1 illustrates a conventional design of a 4T pixel configuration ofa CMOS image sensor connected to a column circuit.

FIG. 2 illustrates a schematic diagram of an exemplary 4T shared pixelCMOS image sensor that can be implemented in connection with anexemplary embodiment.

FIG. 3 illustrates a top-down view of a portion of a pixel arrayaccording to an exemplary embodiment.

FIG. 4 illustrates a block diagram of a conceptual view of a portion ofthe pixel array shown in FIG. 3.

FIGS. 5 and 6 illustrate schematic diagrams of a plurality of 4T sharedpixels in a pixel array of an image sensor according to an exemplaryembodiment.

FIG. 7 is a flowchart of a method of performing digital sampling ofpixel values of a CMOS image sensor.

FIG. 8 illustrates a block diagram of a CMOS image sensor according toan exemplary embodiment.

FIG. 9 illustrates a camera system diagram for dynamic pixel managementof a CMOS image sensor according to an embodiment.

FIG. 10 illustrates a system architecture of a CMOS image sensoraccording to an embodiment.

FIG. 11A illustrates a schematic diagram of a shared pixel unitaccording to an embodiment.

FIG. 11B illustrates a partial cross-sectional device diagram of ashared pixel unit according to the embodiment of FIG. 11A.

FIG. 11C illustrates a symbol diagram of the shared pixel unit accordingto the embodiment of FIG. 11A.

FIG. 12 illustrates features of a column circuit with shared pixel unitsaccording to an embodiment.

FIG. 13A illustrates a control diagram for subtracting noise accordingto an embodiment.

FIG. 13B illustrates a control diagram for subtracting noise accordingto another embodiment.

FIGS. 14A-B illustrate a comparison of a pixel array using an ultra-highdefinition (UHD) resolution mode with a pixel array using a highdefinition (HD) resolution mode according to dynamic pixel management(DPM) embodiments.

FIG. 15A illustrates a pixel timing readout scheme of signalscorresponding to an ultra-high definition (UHD) mode with differentialdigital double sampling (dDDS) according to an embodiment.

FIG. 15B illustrates a pixel timing readout scheme of additional signalscorresponding to the embodiment of FIG. 15A.

FIG. 16A illustrates a partial pixel timing readout scheme of signalscorresponding to an ultra-high definition (UHD) mode with digital doublesampling (DDS) according to an embodiment.

FIG. 16B illustrates a partial pixel timing readout scheme of signalscorresponding to the embodiment of FIG. 16A.

FIG. 17 illustrates a pixel timing readout scheme of signalscorresponding to a high definition (HD) mode with digital doublesampling DDS according to an embodiment.

FIG. 18A illustrates a partial pixel timing readout scheme of signalscorresponding to an HD mode using a global shutter sequence according toan embodiment.

FIG. 18B illustrates a partial pixel timing readout scheme of signalscorresponding to the embodiment of FIG. 18A.

FIG. 19 illustrates a flowchart of dynamic pixel management according toan embodiment.

DETAILED DESCRIPTION

Various aspects of the disclosed system and method are now describedwith reference to the drawings, wherein like reference numerals are usedto refer to like elements throughout. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to promote a thorough understanding of one or more aspects of thedisclosure. It may be evident in some or all instances, however, thatany aspects described below can be practiced without adopting thespecific design details described below. In other instances, well-knownstructures and devices are shown in block diagram form in order tofacilitate description of one or more aspects. The following presents asimplified summary of one or more aspects of the invention in order toprovide a basic understanding thereof.

In one configuration, the number of rows and columns of photodiodes in apixel array of a CMOS image sensor may both be doubled. As a result,there may be four time of photodiodes in an image area compared with thenumber of photodiodes when the image area is filled with 4T pixels. Insuch a configuration, each pixel area that may originally be occupied byone 4T pixel may contain four photodiodes. Such a pixel that containsfour photodiodes may be referred to as a 4T shared pixel, a sharedpixel, and/or a shared pixel unit.

FIG. 2 illustrates a schematic diagram of an exemplary 4T shared pixelCMOS image sensor that can be implemented in connection with anexemplary embodiment. The shared pixel 200 includes a similarconfiguration as the 4T pixel described above except that it includesfour sub-pixels, e.g., photodiodes 210A, 210B, 210C and 210D (also shownas PD0-PD3) that are each driven by a respective transfer gate (shown asTG0-TG3). The transfer gates, which are CMOS transistors, are identifiedby reference numerals 212A, 212B, 212C and 212D. As shown, each of thetransfer gates 212A-112D shares a common readout circuit and isconnected to floating diffusion point, 214, i.e., capacitor C_(fd). Asfurther shown, both transistor 216 (reset transistor) and transistor 217have drains connected to the voltage source of the pixel (e.g., VDDPIX). The source of reset transistor 216 is connected to the floatingdiffusion point 214 and the source of transistor 217 is connected to thedrain of the select transistor 218. The source of select transistor 218is connected to the column circuit 219.

As will be discussed in more detail below, each sub-pixel (i.e., each ofphotodiodes PD0-PD3) can be read out separately by activating itscorresponding transfer gate. Thus, to read out photodiode 210A, thetransfer gate 212A is turned on/activated. Similarly, photodiode 210B isread out by activating transfer gate 212B, and so forth. In someinstances, multiple sub-pixels will be read out at the same time as asingle read operation by activating the respective transfer gatessimultaneously.

In order to take advantage of the higher resolution provided by theshared pixels, each photodiode of a shared pixel may need to be read outindividually. To read out each photodiode of a shared pixelindividually, four wires may be needed to addressed each photodiodesindividually. Having four wires connected to a shared pixel may degradethe performance of the shared pixel, e.g., by blocking the optical pathsof the shared pixel, and/or by detrimentally affecting the conversiongain, fill factor, sensitivity of the image sensor. Thus, it may bedesirable to reduce the interconnection/wiring associated with a sharedpixel while maintaining the capability to read out each photodiode ofthe shared pixel individually.

FIG. 3 illustrates a top-down view of a portion of a pixel array 300according to an exemplary embodiment. The pixel array 300 includes amultitude of shared pixels described above. For example, as shown in themiddle of the exemplary pixel array 300, a shared pixel 302 is shown asa solid dark square and includes sub-pixels (i.e., photodiodes PD0-PD3)identified as photodiodes 310A-310D. As further shown, a shared pixelincluding photodiodes 320A, 320B, 320C and 320D is shown in the arrayrow above the row of the shared pixel 302 and another shared pixelincluding photodiodes 330A, 330B, 330C and 330D is shown in the arrayrow below the row of the shared pixel 302. In one configuration, each ofthe shared pixel 302, and the shared pixels above and below the sharedpixel 302 may be the shared pixel 200 described above in FIG. 2.

According to the exemplary embodiment, the pixel array 300 shows a threeby three array of 4T shared pixels. The pixel array 300 can be a portionof an array with 1125 rows, and each row can comprise two sub-pixels(i.e. photodiodes PD0 and PD2). Thus, each row may comprise verticalshift registers that are two by 1125 lines deep, i.e., 2250 lines.Additionally, because there are a total of four sub-pixels (i.e.photodiodes PD0-PD3), an array with 1125 rows can provide a total of4500 sub-pixel signals or voltages, each of which are to be readout bythe platform and/or camera system using the pixel array 300. A camerasystem or platform using digital double sampling (DDS) may be furtherrequired to readout both a dark signal and a bright signal per image;thus, a platform may be required to readout a total of two times 4500sub-pixel signals (9000 sub-pixel signals) per image. According to theteachings herein, another readout method, differential DDS (dDDS) can beadvantageously used to further reduce the number of required readoutsfrom 9000 to 6750.

As further shown, each of the photodiodes of pixel 302 are connected toits respective transfer gate as described above. Thus, photodiode 310Ais connected to transistor 312A, photodiode 310B is connected totransistor 312B, photodiode 310C is connected to transistor 312C, andphotodiode 310D is connected to transistor 312D. Although pixel 302 isillustrated with a solid line square, the pixel array 300 provides across connection of pixels such that sub-pixels of adjacent pixels areread out concurrently to minimize bandwidth. Each readout is illustratedwith dashed lines and boxes. Thus, the sub-pixels forming the groupingof sub-pixels 306 may be read out first followed by the grouping ofsub-pixels 304, as will become readily apparent based on the followingdisclosure.

Thus, photodiode 310C (PD2) of the shared pixel 302 may be read outconcurrently when photodiode 320B (PD1) of the shared pixel in the rowabove is read out. In one configuration, photodiode 310C (PD2) may beread out during a first clock cycle, and photodiode 320B (PD1) may beread out during a second clock cycle. The first clock cycle and thesecond cycle may be consecutive clock cycles. Similarly, photodiode 310D(PD3) of the shared pixel 302 may be read out concurrently whenphotodiode 320A (PD0) of the shared pixel in the row above is read out.In one configuration, photodiode 310D (PD3) may be read out during afirst clock cycle, and photodiode 320A (PD0) may be read out during asecond clock cycle. The first clock cycle and the second cycle may beconsecutive clock cycles.

Moreover, when photodiode 310A (PD0) of pixel 302 is read out,photodiode 330D (PD3) of the shared pixel in the row below may also getread out. In one configuration, photodiode 310A (PD0) may be read outduring a first clock cycle, and photodiode 330D (PD3) may be read outduring a second clock cycle. The first clock cycle and the second cyclemay be consecutive clock cycles. Similarly, when photodiode 310B (PD1)of pixel 302 is readout, photodiode 330C (PD2) of the shared pixel inthe row below may also get read out. In one configuration, photodiode310B (PD1) may be read out during a first clock cycle, and photodiode330C (PD2) may be read out during a second clock cycle. The first clockcycle and the second cycle may be consecutive clock cycles.

As explained above with reference to FIG. 2, to read out a value of aparticular photodiode, the respective transfer gate must be activated.In this instance, transfer gate signals are applied to sub-pixels inadjacent rows, to read out two values concurrently. For example, asshown a transfer gate signal TG_(0/3) (i.e., signal 340A) is applied totransistor 312A, such that the sub-pixel 310A can be read out as shownabove. As further shown, this transfer gate signal 340A is also appliedto the transfer gate for photodiode 330D on the adjacent row below therow of the shared pixel 302. During the same readout period that thetransfer gate signal 340A is activated, the control circuit alsoactivates transfer gate signal 340B, which activates the transfer gatesfor photodiode 310B of the shared pixel 302 and photodiode 330C (i.e.,PD2) of the shared pixel directly below the shared pixel 302. As shown,transfer gate signal 340A and transfer gate signal 340B are in the samerow of the shift register.

Furthermore, during the next readout period, transfer gate signals 342Aand 342B will be applied in a similar manner. Transfer gate signals 342Aactivates the transfer gates for photodiode 310C of the shared pixel 302and photodiode 320B of the shared pixel directly above the shared pixel302 in the pixel array 300. Similarly, transfer gate signals 342Bactivates the transfer gates for photodiode 310D of the shared pixel 302and photodiode 320A of the shared pixel directly above the shared pixel302 in the pixel array 300.

In one configuration, the interconnections (e.g., 350 and 352) thatcross-couple transfer gates of two different shared pixels may belocated at the edge of the image area, as illustrated in FIG. 4. In oneconfiguration, the interconnections (e.g., 350 and 352) thatcross-couple transfer gates of two different shared pixels may belocated in the pixel grid (e.g., in the shared pixel 302 and the sharedpixel above or below the shared pixel 302), thus reducing the amount ofshift registers on the edge of the image area.

FIG. 4 illustrates a block diagram of a conceptual view of a portion ofthe pixel array shown in FIG. 3. In particular, the column shown in thisfigure includes a shared pixel 400 that includes sub-pixels A_(n),B_(n), C_(n) and D_(n). In one configuration, the shared pixel 400 maybe the shared pixel 200 or 302 discussed above, and the sub-pixelsA_(n), B_(n), C_(n) and D_(n) may correspond to sub-pixels 210A-210D or310A-310D discussed above. Moreover, as described above, each 4T sharedpixel includes a floating diffusion point, which is illustrated asFD_(n) and denoted by 410. As further shown, a shared pixel 402 in thepreceding row is formed by sub-pixels A_(n−1), B_(n−1), C_(n−1) andD_(n−1) (including floating diffusion point FD_(n−1)) and two sub-pixelsC_(n−2) and D_(n−2) are formed above the shared pixel 402. Similarly,the row following the shared pixel 400 includes a shared pixel 406formed by sub-pixels A_(n+1), B_(n+1), C_(n+1) and D_(n+1) (includingfloating diffusion point FD_(n+1)), and two sub-pixels A_(n+2) andB_(n+2) are formed below the shared pixel 406. For purposes of thisdisclosure, the row for each shared pixel can be considered as rows n−2,n−1, n, n+1 and n+2. For example, the shared pixel 400 is on row n, theshared pixel 402 is on row n−1, and the shared pixel 406 is on row n+1.

As described above, each transfer gate is activated for two adjacentsub-pixels in the vertical direction (relative to the array) that are indifferent adjacent pixel rows (e.g., in rows n−1 and n, or in rows n andn+1). Thus, the transfer gates for sub-pixels C_(n−1) and B_(n) mayfirst be activated by transfer gate signal 430B. Since sub-pixelsC_(n−1) and B_(n) are in different rows, i.e., different shared pixels,the values of the sub-pixels C_(n−1) and B_(n) may be read out duringthe same readout period. Next, a transfer gate signal 430A may beapplied to activate sub-pixels A_(n) and D_(n−1). After the activationby the pair of transfer gate signals 430A and 430B, the CMOS imagesensor has performed a readout of sub-pixels A_(n), B_(n), C_(n−1), andD_(n−1). It should be appreciated that this readout may correspond tothe dashed box 306 shown in FIG. 3 in which sub-pixel 310A (e.g.,A_(n)), sub-pixel 310B (e.g., B_(n)), sub-pixel 330C (e.g., C_(n−1)),and sub-pixel 330D (e.g., D_(n−1)), are all read out during one readoutperiod.

Referring back to FIG. 4, during the next cycle of readout, transfergate signals 432B and 432A may be applied to activate the correspondingsub-pixels. In a similar manner as described above, the transfer gatesfor sub-pixels C_(n) and B_(n+1) may first be activated by transfer gatesignal 432B. Next, transfer gate signal 432A may be applied to activatesub-pixels A_(n+1) and D_(n). Accordingly, after the activation by thepair of transfer gate signals 432A and 432B, the CMOS image sensor hasperformed a readout of sub-pixels C_(n), D_(n), A_(n+1) and B_(n+1).

FIGS. 5 and 6 illustrate schematic diagrams of a plurality of 4T sharedpixels in a pixel array of an image sensor according to an exemplaryembodiment. As shown in FIG. 5, the pixel array includes a pair ofadjacent rows, i.e., 1st pixel row n−1 and 2nd pixel row n, in thevertical direction of the pixel array. It should be appreciated thateach separate shared pixel in row n and n−1 includes the same 4T sharedtransistor circuit configuration discussed above with respect to FIG. 2and will not be repeated herein. As shown, one transfer gate signal 530Amay be applied to the transfer gate (TG0) of sub-pixel C_(n−1) and tothe transfer gate (TG3) of sub-pixel B_(n). Similarly, another transfergate signal 530B may be applied to the transfer gate (TG2) of sub-pixelA_(n) and to the transfer gate (TG1) of sub-pixel D_(n−1). In oneconfiguration, the transfer gate signals 530A and 530B may be thetransfer gate signals 340A and 340B, 342A and 342B, 430A and 430B, or432A and 432B described above.

FIG. 6 illustrates the same pixel array circuit diagram as in FIG. 5 andalso shows application of additional transfer gate signals 632A and632B, which are the same transfer gate signals described above. In bothFIGS. 5 and 6, the output of each sub-pixel is connected to the columncircuit to provide readouts.

FIG. 7 is a flowchart 700 of a method of performing digital sampling ofpixel values of a CMOS image sensor. The method may be performed by anapparatus that includes a CMOS image sensor. The CMOS image sensor mayinclude a pixel array, which may include a multitude of shared pixels asdescribed above. At 702, the apparatus may read out a first pixel valuefrom a first pixel (e.g., the shared pixel 400) on a first pixel row byapplying a first signal (e.g., the transfer gate signal 430A) to thefirst pixel. The first pixel may include a first plurality ofphotodiodes. The first pixel value from the first pixel may be read outfrom a first one of the photodiodes of the first plurality ofphotodiodes (e.g., A_(n)).

At 704, The apparatus may read out a first pixel value from a secondpixel (e.g., the shared pixel 402) on a second pixel row by concurrentlyapplying the first signal (e.g., the transfer gate signal 430A) to thesecond pixel. The second pixel may include a second plurality ofphotodiodes. The first pixel value from the second pixel may be read outfrom a first one of the photodiodes of the second plurality ofphotodiodes (e.g., D_(n−1)).

In one configuration, the first pixel row may be adjacent to the secondpixel row, and the first pixel may be adjacent to the second pixel. Inone configuration, the first one of the photodiodes of the firstplurality of photodiodes (e.g., A_(n)) and the first one of thephotodiodes of the second plurality of photodiodes (e.g., D_(n−1)) maybe on different columns. In one configuration, the first pixel valuefrom the first pixel may be read out during a first clock cycle, and thefirst pixel value from the second pixel may be read out during a secondclock cycle. The first clock cycle and the second clock cycles may beconsecutive clock cycles.

At 706, the apparatus may optionally read out a second pixel value fromthe first pixel (e.g., the shared pixel 400) by applying a second signal(e.g., the transfer gate signal 430B) to the first pixel. The secondpixel value from the first pixel may be read out from a second one ofthe photodiodes of the first plurality of photodiodes (e.g., B_(n)).

At 708, the apparatus may optionally read out a second pixel value fromthe second pixel (e.g., the shared pixel 402) by concurrently applyingthe second signal (e.g., the transfer gate signal 430B) to the secondpixel. The second pixel value from the second pixel may be read out froma second one of the photodiodes of the second plurality of photodiodes(e.g., C_(n−1)).

In one configuration, the second one of the photodiodes of the firstplurality of photodiodes (e.g., B_(n)) and the second one of thephotodiodes of the second plurality of photodiodes (e.g., C_(n−1)) maybe on different columns. In one configuration, the second pixel valuefrom the first pixel may be read out during a first clock cycle, and thesecond pixel value from the second pixel may be read out during a secondclock cycle. The first clock cycle and the second clock cycles may beconsecutive clock cycles.

In one configuration, the apparatus may include a first row of pixelsincluding a first pixel (e.g., the shared pixel 402). The first pixelmay include a first plurality of photodiodes and a first plurality oftransfer gates. Each of the first plurality of photodiodes may beassociated with a corresponding one of the first plurality of transfergates. The apparatus may include a second row of pixels including asecond pixel (e.g., the shared pixel 400). The second pixel may includea second plurality of photodiodes and a second plurality of transfergates. Each of the second plurality of photodiodes may be associatedwith a corresponding one of the second plurality of transfer gates. Afirst one of the transfer gates of the first plurality of transfer gates(e.g., the transfer gate associated with D_(n−1)) may be coupled to afirst one of the transfer gates of the second plurality of transfergates (e.g., the transfer gate associated with A_(n)).

In one configuration, the connection for coupling the first one of thetransfer gates of the first plurality of transfer gates (e.g., thetransfer gate associated with D_(n−1)) and the first one of the transfergates of the second plurality of transfer gates (e.g., the transfer gateassociated with AO may be at the edge of an image area. The image areamay include the first row of pixels and the second row of pixels. In oneconfiguration, the connection for coupling the first one of the transfergates of the first plurality of transfer gates (e.g., the transfer gateassociated with D_(n−1)) and the first one of the transfer gates of thesecond plurality of transfer gates (e.g., the transfer gate associatedwith A_(n)) may be at the first pixel (e.g., the shared pixel 402) andthe second pixel (e.g., the shared pixel 400).

In one configuration, a first one of the photodiodes of the firstplurality of photodiodes (e.g., D_(n−1)) may be associated with thefirst one of the transfer gates of the first plurality of transfergates, and a first one of the photodiodes of the second plurality ofphotodiodes is associated with the first one of the transfer gates ofthe second plurality of transfer gates (e.g., A_(n)). In oneconfiguration, the first one of the photodiodes of the first pluralityof photodiodes (e.g., D_(n−1)) and the first one of the photodiodes ofthe second plurality of photodiodes (e.g., A_(n)) may be on differentcolumns. In one configuration, the first row of pixels may be adjacentto the second row of pixels. The first pixel may be adjacent to thesecond pixel.

In one configuration, a second one of the transfer gates of the firstplurality of transfer gates (e.g., the transfer gate associated withC_(n−1)) may be coupled to a second one of the transfer gates of thesecond plurality of transfer gates (e.g., the transfer gate associatedwith B_(n)). In one configuration, the connection for coupling thesecond one of the transfer gates of the first plurality of transfergates (e.g., the transfer gate associated with C_(n−1)) and the secondone of the transfer gates of the second plurality of transfer gates(e.g., the transfer gate associated with B_(n)) may be at the edge of animage area. The image area may include the first row of pixels and thesecond row of pixels. In one configuration, the connection for couplingthe second one of the transfer gates of the first plurality of transfergates (e.g., the transfer gate associated with C_(n−1)) and the secondone of the transfer gates of the second plurality of transfer gates(e.g., the transfer gate associated with B_(n)) may be at the firstpixel (e.g., the shared pixel 402) and the second pixel (e.g., theshared pixel 400).

In one configuration, the apparatus may further include a third row ofpixels comprising a third pixel (e.g., the shared pixel 406). The thirdpixel may include a third plurality of photodiodes and a third pluralityof transfer gates. Each of the third plurality of photodiodes may beassociated with a corresponding one of the transfer gates of the thirdplurality of transfer gates.

In one configuration, the second row of pixels may be adjacent to thethird row of pixels, and the second row of pixels may be located betweenthe first row of pixels and the third row of pixels. In oneconfiguration, the second pixel (e.g., the shared pixel 400) may beadjacent to the third pixel (e.g., the shared pixel 406). In oneconfiguration, the second pixel (e.g., the shared pixel 400) may belocated between the first pixel (e.g., the shared pixel 402) and thethird pixel (e.g., the shared pixel 406).

In one configuration, a third one of the transfer gates of the secondplurality of transfer gates (e.g., the transfer gate associated withC_(n)) may be coupled to a first one of the transfer gates of the thirdplurality of transfer gates (e.g., the transfer gate associated withB_(n+1)). In one configuration, a fourth one of the transfer gates ofthe second plurality of transfer gates (e.g., the transfer gateassociated with D_(n)) may be coupled to a second one of the transfergates of the third plurality of transfer gates (e.g., the transfer gateassociated with A_(n+1)). In one configuration, the connection for crosscoupling the transfer gates may be at the edge of an image area. Theimage area may include the second row of pixels and the third row ofpixels. In one configuration, the connection for cross coupling thetransfer gates may be at the second pixel (e.g., the shared pixel 400)and the third pixel (e.g., the shared pixel 406).

FIG. 8 illustrates a block diagram of a CMOS image sensor according toan exemplary embodiment. As shown, the CMOS image sensor 800 includes apixel array 810, which can be, for example, pixel array 300 describedabove that includes a multitude of 4T shared pixel configurations.Furthermore, the output of the pixel array 810 may be fed to an analogreadout path and A/D converter 820, which is provided for processing theanalog output voltages from the pixel array 810 to convert analog pixelsignals into digital signals. It should be understood that the analogreadout path and A/D converter 820 is known to those skilled in the art.

As further shown, a latch array unit (or line buffer) 830 is providedfor storing the digital signals outputted from the analog readout pathand A/D converter 820. It should be appreciated that the line buffer 830can include multiple lines depending on the readout order of the pixelsof pixel array 810. Moreover, a control unit 850 is provided forproviding control signals used in controlling the aforementioned unitsand outputting data to the outside (e.g., a display unit) through aninterface. For example, the control unit 850 in conjunction with rowdecoder 840 can generate the activating signals. Moreover, in oneembodiment, the control unit 850 can also generate the control signalsto open and close the switches of the capacitor readout.

The control unit 850 may include one or more processors and one or moremodules for executed the control algorithms described herein. Themodules may be software modules running in the processor, orresident/stored in memory, one or more hardware modules coupled to theprocessor, or some combination thereof. Examples of processors includemicroprocessors, microcontrollers, digital signal processors (DSPs),field programmable gate arrays (FPGAs), programmable logic devices(PLDs), state machines, gated logic, discrete hardware circuits, andother suitable hardware configured to perform the various functionalitydescribed throughout this disclosure. One or more processors in theprocessing system may execute software. Software shall be construedbroadly to mean instructions, instruction sets, code, code segments,program code, programs, subprograms, software modules, applications,software applications, software packages, routines, subroutines,objects, executables, threads of execution, procedures, functions, etc.,whether referred to as software, firmware, middleware, microcode,hardware description language, or otherwise.

Furthermore, the control unit 850 may be coupled to a row decoder 840that is configured to output the signals for selecting the rows in thepixel array 810 based on a control signal transmitted from the controlunit 850. Moreover, the control unit can include an image generatingunit configured to generate image data (i.e., the “data output”) basedon the stored sampled output values in the plurality of storagecapacitors, i.e., the received “data signal”, of which the generatedimage can be configured to be displayed on a display device as should beappreciated to one skilled in the art.

Preferably, the analog readout path and A/D converter 820 may includecomparators as many as the number of columns of the pixel array 810 asdescribed above. Each of the comparators serves a role of converting ananalog pixel value of a column in which it is located into a digitalsignal. The digital signal is stored in the latch array unit 830including latches as many as the number of the columns of the pixelarray 810. The digital signals stored in the latch array unit 830 aresubjected to an image processing by the control unit 850 and then,sequentially outputted through output pins of the image sensor in theimage processed order.

According to the disclosure herein, the exemplary method and sensorprovide for an efficient readout of pixel values from a pixel array thatreduces the required output bandwidth and enables digital doublesampling through the whole analog chain of the pixel array. Moreover,using the disclosed technique, effects like Black sun and fluctuatinganalog disturbances are avoided and suppressed.

In one configuration, to reduce interconnections in the pixel or pixelarray, two transfer gates belonging to two different shared pixels(e.g., two shared pixels on two adjacent rows) may be connected. As aresult, two floating diffusions of the two shared pixels are read out atthe same time (e.g., during the same readout period). By cross couplingtwo transfer gates on two different rows, two shared pixels may beoperated in parallel. This configuration may reduce the amount of wiringneeded for the vertical shift registers for addressing the pixels orsub-pixels. For example, for a shared pixel with four photodiodes, thenumber of interconnections to address the shared pixel may be reducedfrom four wires to two wires. With reduced wiring in the shared pixel,the pixel performance (e.g., conversion gain, fill factor, sensitivityof the shared pixel) may improve due to lower complexity in wiring.

It should be appreciated that in the examples above, all switchingsignals are assumed to be positive logic signals, i.e. a high level, or“1” results in closing the switch. It is, however, also possible to usean inverted logic, or to use both, positive and negative, logic in amixed manner. Moreover, the disclosed CMOS image sensor and methodprovides an increased speed of the overall readout circuit. In oneaspect, the increase in the speed of the readout circuit allows for anincrease in the number of pixels in a matrix, which is a key feature forhigh definition imaging.

Dynamic Pixel Management of a CMOS Image Sensor

Camera resolution and shutter operation determine, in part, the qualityof a camera. Camera resolution can be related to the number of pixelsused to capture an image while shutter operation can relate to how theexposed information is processed or read into memory. Camera resolutioncan further be classified into standards. For instance, a highdefinition (HD) standard can be based on a pixel area count of 1,920 by1080 compared to an ultra-high definition (UHD) standard based on apixel area count of 4,096 by 2160. Notably the UHD standard is alsoreferred to as 4K-UHD and is four times the HD standard. Additionally,operating a camera for UHD as compared to operating a camera for HD candemand higher read rates when the camera uses a CMOS image sensor.

Shutter operation can be categorized by either a rolling line shuttersequence or a global shutter sequence. During a rolling shutteroperation in a CMOS image sensor, the rows of a pixel array can beexposed and read sequentially; thus, there is delay between consecutiverows. The delay can, in turn, lead to picture distortion when the rateof the rolling shutter exposure and/or capture sequence is lower thanthe rate of the moving object. Global shutter can alleviate thedistortion problem by exposing and storing all pixel data concurrently(globally). However, due to the way in which exposed pixels must be readrow-by-row from a CMOS pixel array, successfully implementing globalshutter with high signal to noise ratios can place a high demand onoverall system bandwidth.

Due to the technical tradeoffs between system bandwidth and capturingmoving images, a camera, video apparatus, and camera system is disclosedthat offers all features of UHD, HD, rolling shutter, and global shutterwith the functionality to convert from one resolution to another. Thus,as will be described in detail below, an apparatus and method fordynamic pixel management (DPM) of a cross pixel interconnected CMOSimage sensor are disclosed. In the exemplary aspects, the cross pixelinterconnected CMOS image sensor can be used as described above in FIGS.2-6, to provide a camera system that provides an advanced DPM scheme forcombining HD, UHD, rolling shutter, and global shutter.

FIG. 9 illustrates a camera system diagram 900 for dynamic pixelmanagement of a CMOS image sensor 902 according to an embodiment. Thecamera system diagram 900 includes an interface 906, a dynamic pixelmanagement (DPM) module 904, and the CMOS image sensor 902. The DPMmodule 904 includes a resolution sub-block 908 and a shutter modesub-block 910. A user can select a camera feature and/or option via theinterface 906. The interface 906 can allow the user to enter a featureselection via an external control panel or via an integrated cameramenu. Based on information provided by the user, the DPM module 904 andthe sub-blocks 908, 910 can control the CMOS image sensor 902 totransfer and read pixels according to an HD or UHD resolution mode andaccording to a rolling shutter or global shutter exposure sequence.Effectively, the interface 906 and/or dynamic pixel manager 904, cancollectively operate as a camera mode controller configured to switchthe camera between a selected UHD mode and a HD mode based on a selectedimage resolution for an image capture. In turn, as will be described indetail below, the image sensor individually samples sub-pixels of eachpixel in an image sensor when the camera mode controller sets the camerato the UHD mode for the image capture and collectively samples thesub-pixels of each pixel in the image sensor when the camera modecontroller sets the camera to the HD mode for the image capture.

The camera user can additionally choose a video format based, at leastin part, on active lines and video modes. An exemplary camera using DPMcan include selections for a plurality of video formats including1080P50, 1080P59, 1080P150, 1080P179, 1080i300, 1080i359, 4K50, and4K50. Here 1080, 4K, “P”, and “i” can represent HD pixels (1080), 4K-UHDpixels (4096), “Progressive”, and “interlaced,” while the numbersincluding 50, 59 can relate to framerates.

FIG. 10 illustrates a system architecture of a CMOS image sensor 902according to an embodiment. The CMOS image sensor 902 includes a dynamicpixel manager or DPM module 1004, vertical circuitry 1006, a CMOS imagesensor array 1008, and horizontal circuitry. The CMOS image sensor array1008 can be a cross pixel interconnected sensor array as describedherein and can also be referred to as a shared pixel sensor array. TheDPM module 1004 can receive one or more signals indicating a userselected “Mode”. For instance, the user may select a camera feature“Mode” from the plurality video formats 1080P50, 1080P59, 1080P150,1080P179, 1080i300, 1080i359, 4K50, and/or 4K50, as described above.

The DPM module 1004 can be realized with one or more elements within theCMOS image sensor to control sub-pixels of the CMOS image sensor array1008. For instance, when the user selects 4K50, the DPM module 1004 candetermine the operation mode (i.e., HD vs. UHD as selected for thepreferred resolution of the captured image, for example) provide controlsignals to the vertical circuitry 1006 and to the horizontal circuitry1010 so that sub-pixels of the CMOS image sensor array 1008(photodiodes) are read sequentially and in a rolling shutter mode.Alternatively, if a video format indicating an HD “Mode” is selected,then the DPM module 1004 can provide signals to the vertical circuitry1006 and to the horizontal circuitry 1010 so that sub-pixels of the CMOSimage sensor array 1008 (photodiodes) are binned together and read ineither a rolling shutter or horizontal shutter mode.

According to the exemplary aspect, the dynamic pixel manager canimplement a number of controllers, include a UHD mode controller and aHD mode controller that are configured to perform the pixel (sub-pixelor photodiode) sampling as described herein. For example, the UHD modecontroller can be configured to control the plurality of vertical andhorizontal charge circuitry to sequentially transfer charge between theat least two photodiodes and the shared floating diffusion of eachshared pixel unit when the dynamic pixel manager sets the operationalmode of the CMOS image sensor to the UHD mode to individually sampleoutput values of each of the at least two photodiode during the imagecapture by the image sensor. Moreover, the HD mode controller configuredto control the plurality of vertical and horizontal charge circuitry tobin charge concurrently between the at least two photodiodes and theshared floating diffusion of each shared pixel unit when the dynamicpixel manager sets the operational mode of the CMOS image sensor to theHD mode to collectively sample output values of each shared pixel unitthat combines output values of the at least two photodiodes during theimage capture by the image sensor. In one exemplary aspect, thesecontrollers can be implemented as part of control unit 850 describedabove.

Although the system architecture of the CMOS image sensor 902 shows anarchitecture having four system blocks (the DPM module 1004, thevertical circuitry 1006, the horizontal circuitry 1010, the CMOS imagesensor array 1008), other configurations are possible. As one ofordinary skill in the art can appreciate, the vertical circuitry 1006can comprise circuit blocks for controlling rows of the CMOS imagesensor array 1008 and the horizontal circuitry 1010 can comprise circuitblocks for reading and processing columns of the CMOS image sensor array1008. For instance, vertical and horizontal circuitry 1006, 1010 caninclude shift registers. Also, horizontal circuitry 1010 can includenoise cancellation circuitry for use with digital double sampling andcan also include analog to digital (A/D) converters, digital signalprocessors (DSPs), memory, and the like. The horizontal circuitry canprovide output data “OUT” in a format suitable for reading in digitaland analog formats.

The DPM module 1004 can include timing circuit blocks including but notlimited to phase locked loops (PLLs) and serial/parallel interfacecomponents. In other configurations timing circuit blocks including PLLscan be external to the DPM module 1004. As one of ordinary skill in theart can appreciate, DPM functionality, as represented by the DPM module1004, can be implemented with both software and hardware and can berealized with one or more circuit components including microprocessorsand/or controllers.

FIG. 11A illustrates a schematic diagram of a shared pixel unit 1100according to an embodiment. A 4T shared pixel sensor can also bereferred to as a shared pixel unit 1100; and the shared pixel unit 1100can be equivalent to the exemplary 4T shared pixel CMOS image sensor ofFIG. 2. However, the components and signal inputs have been arranged tofacilitate discussion of timing diagrams. The shared pixel unit 1100includes sub-pixels An, Bn, Cn, and Dn, each electrically coupledbetween ground and a storage node of floating diffusion FDn for an N-throw (n-th row) within a shared pixel array. As shown in FIG. 11A, thefloating diffusion FDn is modeled as a capacitor C_(fd). Also, thestorage node is electrically coupled to a source of reset transistor MN5and to a gate of source follower transistor MN6. The select transistorMN7 is coupled between the source of transistor MN6 and the column buss“COLUMN”.

The sub-pixels An, Bn, Cn, and Dn, are shared pixel units and eachincludes a photodiode (PD0-PD3) and a gate transistor (MN0-MN3). Asdiscussed above with respect to FIG. 2 and as shown in FIG. 11A, thegate nodes (gates) of transistors (MN0-MN3) each receive a transfer gatesignal TG0(N)-TG3(N). Also, the gate of reset transistor MN5 receives areset signal RST(N) and the gate of the read select transistor MN7receives a select signal SEL(N). The index “N” indicates the signals areapplied to the gates of the pixel array unit of row N (row n). Asdetailed in FIG. 11B, each sub-pixel An, Bn, Cn, and Dn, can be realizedby a composite layout of a gate between the floating diffusion FDn and adiffusion of a photodiode (PD0-PD3).

FIG. 11B illustrates a partial cross-sectional device diagram 1103 of ashared pixel unit according to the embodiment of FIG. 11A. The partialcross-sectional device diagram 1103 shows includes a simplified crosssection representation of diffusions 1105, 1106, 1107 and interconnectrelating to sub-pixels Cn, Dn and floating diffusion FDn. In FIG. 11Bthe diffusions 1105 and 1107 can represent N-type diffusions ofphotodiodes PD0 and PD1, respectively forming junctions in P-epitaxiallayer 1108; and diffusion 1106 can represent the N-type diffusionforming a storage depletion layer capacitor C_(fd) in floating diffusionFDn. As shown in FIG. 11B, transistor MN0 can be formed by the gate 1114between diffusions 1105 and 1106, and transistor MN1 can be formed bythe gate 1112 between diffusions 1107 and 1106.

As one of ordinary skill in the art can appreciate, when the gate TG0(N)receives a signal or voltage causing an inversion region betweendiffusions 1105 and 1106, charge can be transferred between thediffusions 1105 and 1106. Similarly, when the gate 1114 receives asignal or voltage TG1(N) causing an inversion region between diffusions1107 and 1106, charge can transferred between the diffusions 1107 and1106. Referring to FIG. 11A, it can be said that charge is transferredbetween photodiode PD0,1 and the floating diffusion FD_(n) when thetransfer gates exert a logic “high”.

FIG. 11C illustrates a symbol diagram 1120 of the shared pixel unitaccording to the embodiment of FIG. 11A. The symbol diagram 1120 shows ahierarchical schematic symbol representation of the schematic of FIG.11A. As one of ordinary skill in the art can appreciate, the symboldiagram can be a convenient way to show the sub-pixels and theirconnection with the gating signals TG0(N)-TG3(N), the row select signalSEL(N), and the row reset signal RST(N).

FIG. 12 illustrates features of a column circuit 1200 with shared pixelunits according to an embodiment. The column circuit 1200 of FIG. 12 canbe equivalent to the conceptual view of the pixel array portion of FIG.4, except further details of the signals have been included tofacilitate discussion of the timing diagrams; also, FIG. 4 introducesnoise cancellation circuitry. The column circuit 1200 of FIG. 12 showsthree pixel array units for rows N−1, N, and N+1, (also referred to inthe lower-case as rows n−1, n, and n+1). The row N−1 pixel array unitincludes sub-pixels A_(n−1), B_(n−1), C_(n−1), and D_(n−1). The row Npixel array unit includes sub-pixels A_(n), B_(n), C_(n), and D_(n); andthe row N+1 pixel array unit includes sub-pixels A_(n+1), B_(n+1),C_(n+1), and D_(n+1).

Similar to the column circuit of FIG. 4, the pixel array units for theN−1, N, and N+1 rows have a crisscross interconnect patternadvantageously allowing gate signals to be combined. As shown in FIG.12, the transfer gate signals have been combined. For instance, thesub-pixel A_(n+1) and the sub-pixel D_(n) are shown to receive a signalTG1/2 (combining TG1(N+1) with TG2(N)), and the sub-pixel B_(n+1) andthe sub-pixel C_(n) are shown to receive a signal TG0/3 (combiningTG0(N) with TG3(N+1)). As can be understood from the timing diagrams, asubscript for the rows has been dropped in the labelling. For instance,as will be explained with respect to the timing diagrams, the signalTG1/2 corresponding to sub-pixels A_(n+1) and D_(n) can be sequencedindependently of the signal TG1/2 corresponding to sub-pixels A_(n) andD_(n−1). Similarly, the signal TG0/3 corresponding to sub-pixels B_(n+1)and C_(n) can be sequenced independently of the signal TG0/3corresponding to sub-pixels B_(n) and C_(n−1).

FIG. 12 also shows a switched capacitor approach for providingdifferential digital double sampling (dDDS) and digital double sampling(DDS). As shown, the circuit includes four capacitors CD1, CD2, CB1 andCB2 that are provided to store the video level and the dark level forthe digital double sampling. In particular, two “bright” capacitors(i.e., capacitors CB1 and CB2) are provided to sample the video leveland two “dark” capacitors (i.e., capacitors CD1 and CD2) are provided tosample the reference level. Thus, as shown, capacitors CD1 and CD2 arecoupled to a capacitor reference voltage to readout a fixed value fromthe reference voltage while capacitors CB1 and CB2 are coupled to thebitline (column m) of the pixel array to sample the pixel voltages ofthe dark, bright and double bright values of each pixel output (i.e.,the video level). The readout path is fully differential and theconnection of each capacitor depends on the mode of operation as will bedescribed in detail below.

At the end of column line (column m), there are two switches, 621A and621B for selectively connecting the output of the pixel array to storagecapacitors CB1 and CB2 to sample the dark, bright and double brightvalues, respectively, from the pixel array. Moreover, the readoutcircuit includes are two more switches, 611A and 611B for selectivelyconnecting the storage capacitors CD1 and CD2 to a reference voltage forthe capacitors. Each of the capacitors CB1, CB2, CD1 and CD2 isrespectively connected in parallel to a reset switch 631A, 631B, 631Cand 631D, in order to reset the capacitors to a previous value to GND(ground). Moreover, column selection switches 641A-641D are respectivelyprovided between the storage capacitors and a bus bar (not shown) thatultimately outputs the measured differential voltages to an A/Dconverter (also not shown) and then to a buffer. Thus, the columnselection switches 641A-641D are controlled to output stored signalsfrom storage capacitors CD1, CD2, CB1 and CB2 to one of the columns at atime to the bus bar. Each of the pixels is activated at a given time bya row decoder.

Advantageously, using this design, the sampling of the pixel outputvoltage from the pixel array is decoupled from the A/D conversion. Thedecoupling enables high speed readout of the pixel output voltages byputting these two actions in parallel instead of serial operation.

FIG. 13A illustrates a control diagram 1300 for subtracting noiseaccording to an embodiment. The control diagram 1300 includes memory1302 and a summing block 1304 for using a DDS scheme. The memory 1302receives a digital representation of a dark (DARK) and/or a bright(BRIGHT) signal. The dark signal can be a digital symbol representationof column data read following a reset of a pixel and prior to exposureof a sub-pixel photodiode. A bright signal can represent a digitalsymbol representation of column data read following the exposure andtransfer of charge between a photodiode and floating diffusion within ashared pixel unit. After a floating diffusion is reset, a value (DARK)is sampled on a column, such as column m of FIG. 11A, and stored on acolumn capacitor. An analog to digital converter can convert the signaland the digital symbol can then be stored into the memory 1302. After atransfer pulse (TG) such as TG0/3 or TG1/2 is exerted, a bright signalfrom the floating diffusion is again read out (BRIGHT) and the twovalues are subtracted at the summing block 1304 to provide a reducednoise video signal (Video PD). This can advantageously remove noise andadditional components of random and systematic offset inherent inelectronic systems. The control diagram 1300 can be implemented in a DSPand/or controller using digital symbols from A/D conversion of analogpixel data. The pixel data can be pixel data read from the columns suchas column m of FIG. 12.

FIG. 13B illustrates a control diagram 1350 for subtracting noiseaccording to another embodiment. The embodiment of FIG. 13B is similarto that of FIG. 13A except the control diagram 1350 includes anadditional summing junction to implement differential DDS. The controldiagram 1350 includes memory 1352, a summing block 1354, and a summingblock 1356 to implement a differential DDS (dDDS) scheme. The memory1352 is shown to receive a digital representation of a dark (DARK),bright (BRIGHT), and double bright (DOUBLEBRIGHT) signal. A brightsignal can represent a digital symbol representation of column data readfollowing the exposure and transfer of charge between a photodiode andfloating diffusion within a shared pixel unit. After a floatingdiffusion is reset, a value (DARK) is sampled on a column, such ascolumn m of FIG. 11A, and stored on a column capacitor. An analog todigital converter can convert the signal which is then stored into thememory 1352.

After a transfer pulse (TG) such as TG0/3 or TG1/2 is exerted, a brightsignal from the floating diffusion is again read out (BRIGHT) and thetwo values are subtracted at the summing block 1354 to provide a reducednoise video signal (Video PD0). Following the read of the bright signal,another read operation can be performed to read out another sub-pixelsuperimposed upon the previous bright (BRIGHT) signal to provide adouble bright (DOUBLEBRIGHT) signal. The bright signal can then besubtracted from the double bright signal in summing block 1356 toprovide a second reduced noise video signal (Video PD1). Thisadvantageously provides two reduced noise signals; and the timingsequence for differential DDS (dDDS) can advantageously reduce theoutput raw data rate. Instead of requiring twice the data-rate ascompared to an analog double sampling readout scheme, the dDDS schemecan reduce the output raw data rate by using the Dark, Bright and DoubleBright values to reconstruct two pixels Video PD0 and Video PD1 withreset-noise suppression each.

FIGS. 14A-B illustrate a comparison of a pixel array 1400 using anultra-high definition (UHD) resolution mode with a pixel array 1420using a high definition (HD) resolution mode according to dynamic pixelmanagement (DPM) embodiments. As illustrated by the pixel array unit1402, in UHD mode the sub-pixels A_(n−1), B_(n−1), C_(n−1) and D_(n−1)can be transferred to their floating diffusion point FD_(n−1) forindividual readout along a column bit-line (column). As depicted, thisallows a four times higher spatial resolution compared to the HD readoutmode of pixel array 1420. In UHD mode readout can be either use DDS ordDDS.

Pixel array 1420 depicts pixel binning. As illustrated by the pixelarray unit 1422, in HD mode the sub-pixels A_(n−1), B_(n−1), C_(n−1) andD_(n−1) can be transferred (binned) to their floating diffusion pointFD_(n−1) concurrently for a combined sub-pixel readout along a columnbit-line (column). The sub-pixels are binned in parallel to create alarger pixel having effectively four times the area of a sub-pixel. Thiscan advantageously provide for a better pixel with more exposure surfacearea at the expense of lower overall pixel resolution. In pixel binning,four photo diodes are readout at once. Charge from four photo diodes isare binned (collected) at the floating diffusion node FD_(n−1).

Charge domain binning can increase sensitivity proportional to thenumber of pixels binned. In the pixel array 1420 configured for HDreadout, the pixel read noise can be the same as the read noise in thepixel array 1400. Thus, there can be an increase in performance by afactor of four. In addition the read-out speed can also increase by afactor of four, since one instead of four pixels are read.Advantageously, in HD mode both global shutter and rolling shuttersequencing can be implemented.

FIG. 15A illustrates a pixel timing readout scheme 1500 of signalscorresponding to an ultra-high definition (UHD) mode with differentialdigital double sampling (dDDS) according to an embodiment. FIG. 15Billustrates the pixel timing readout scheme 1570 of additional signalscorresponding to the embodiment of FIG. 15A.

The readout schemes 1500, 1570 can illustrate horizontal timing of apixel array having a crisscross interconnect pattern for providingdifferential digital double sampling. As shown, the horizontal readoutschemes 1500, 1570 can be based on a counter to provide cycles of sixsub-counts as indicated by signal “4K SubCnt”. The timing diagram timeaxis is therefore shown to be partitioned into counter based cycleslabelled 1520-1542. In this regard, the counter performs the countoperation in synchronization with clocks having a fixed period; forinstance, a shift register clock signal “ShiftRegClk” is shown toprovide a clock pulse every six cycles. Also, in regard to the counterbased cycles, during each cycle 1520-1542 a column capacitor is resetvia the signal “RST_CCAP”.

In one embodiment, the readout can performed in accordance with the1080p standard with each readout (i.e., each clock cycle) beingperformed at 14.81 μs as indicated by the VC signal index. After eachreadout cycle, there can be six values that are obtained, two darkvalues, two bright values, and two double bright values. After thedifferential digital double sampling technique is applied using thesevalues, corrected digital outputs of four pixels can be obtained, whichgenerates a 4 k/UHD standard.

For purposes of illustration, the timing diagram is annotated inaccordance with the sub-pixels illustrated in FIG. 12 discussed above.As shown, during a first count value 1520, a reset signal Rst1 can beapplied to a row n−1, and more particularly, to reset a floatingdiffusion fd_(n−1) (FD_(n−1)). Preferably, the reset signals have awidth of 22 clocks at 222 MHz or 99 nanoseconds. During this same count,a select signal Sel1 is applied to row n−1, i.e., D_(n−1). Preferably,the select signals have a width of 210 elks at 222 MHz or 943nanoseconds. Similarly, during a second count value 1522, a reset signalRst2 is applied to row n, i.e., to floating diffusion point fd_(n)(FD_(n)) and a select signal Sel2 is applied to row n, i.e., to D_(n).Thus, it should be appreciated that in accordance with the dDDSfiltering technique, each of rows n−1 and n have been reset such thatdigital data for each pixel can obtained. This is shown in the readoutrow (i.e., “READ”) in which the dark values R_(n−1) and R_(n) are readout from the pixel array during counts 2 and 3 of the clock cycle.

In general, the timing diagram illustrates that the capacitors are resetby RST_CCAP value at the top of each count and the control signal SW_Bfor capacitors CB1 and CB2 and the control signal SW_D for capacitorsCD1 and CD2 are continuously applied to sample the date on the bitline(column) as should be understood to those skilled in the art. Theresetting and sampling of these capacitors will not be described foreach separate count in the cycle.

Once the dark values R_(n−1) and R_(n) are sampled at counts 1 and 2(count period 1520 and 1522), and readout at counts 2 and 3 (1522 and1523), the timing continues to count 3 (1523) of the cycle. As shown, atransfer gate TG0/3 is applied to activate the corresponding sub-pixelin rows n−1 and n. For example, this transfer gate signal TG0/3 canactivate sub-pixels C_(n−1) and B_(n). Thus, when select signal Sel1 isapplied again to row n−1, sub-pixel C_(n−1) can be readout as furthershown during count 4 (1526). Similarly, when select signal Sel2 isapplied again to row n, sub-pixel B_(n) can be readout as further shownduring count 5 (1528). Preferably, the transfer gate signals have awidth of 320 clocks at 222 MHz or 1437 nanoseconds.

Furthermore, during count 5 (1528), a transfer gate TG1/2 can be appliedto activate the corresponding sub-pixels in row n and n−1. This transfergate signal TG1/2 can activates sub-pixels D_(n−1) and A_(n). Thus, whenselect signal Sel1 is applied again to row n−1, a double bright value ofboth sub-pixel C_(n−1) and D_(n−1) can be readout as further shownduring count 6 (1530). Similarly, when select signal Sel2 is appliedagain to row n, a double bright value of sub-pixel B_(n) and sub-pixelA_(n) can be readout as further shown during count 1 of the next clockcycle (1532). Accordingly, during this counter cycle, the readoutcircuit has sampled values from sub-pixels C_(n−1) and B_(n) and doublebright values from sub-pixels C_(n−1) and D_(n−1) and from sub-pixelsA_(n) and B_(n). As described above with respect to FIGS. 13A and 13B,the values for sub-pixels D_(n−1) can be determined by removing thevalue of C_(n−1) from the double bright value. Similarly, the values forsub-pixels A_(n) can be determined by removing the value of B_(n) fromthe double bright value.

FIG. 16A illustrates a partial pixel timing readout scheme 1600 ofsignals corresponding to an ultra-high definition (UHD) mode withdigital double sampling (DDS) according to an embodiment. FIG. 16Billustrates a partial pixel timing readout scheme 1670 of signalscorresponding to the embodiment of FIG. 16A. Unlike the readout schemes1500, 1570, the readout schemes 1600, 1670 show timing diagrams for DDSwhich is portioned over eight cycles instead of six. The timing diagramtime axis, portioned over counter based cycles labelled 16 is thereforeshown to be partitioned into counter based cycles labelled 1620-1650. Inthis regard, the counter performs the count operation in synchronizationwith clocks having a fixed period; for instance, a shift register clocksignal “ShiftRegClk” is shown to provide a clock pulse every eightcycles.

As shown in the readout schemes 1600 and 1670, over a period of eightcycles (1620-1634) of 1.85 us duration, DDS can be implemented in UHDmode. Referring to the “Read” data, the DDS cycles can be implemented soas to read a dark value R_(n−1) during cycle 2 (1622), a dark valueR_(n) during cycle 3 (1624), a bright value C_(n−1) during cycle 4(1626), and a bright value B_(n) during cycle 5 (1628). The dark valueR_(n−1) can be subtracted from the bright value C_(n−1), and the darkvalue R_(n) can be subtracted from the bright value B_(n) using DDS asdepicted in FIG. 13A. As shown, this process of reading in sequence aDark, Dark, Bright, and Bright signal continues until a total of sevensub-pixel C_(n−1), B_(n), D_(n−1), A_(n), C_(n), B_(n+1), D_(n). andB_(n) are read. In this way DDS can be applied each of the sevensub-pixel C_(n−1), B_(n), D_(n−1), A_(n), C_(n), B_(n+1), D_(n). andB_(n) values.

FIG. 17 illustrates a pixel timing readout scheme 1700 of signalscorresponding to a high definition (HD) mode with digital doublesampling DDS according to an embodiment. The pixel timing readout scheme1700 shows a timing scheme where sub-pixels are binned concurrently andDDS is applied to the read values. As shown the readout scheme 1700 canbe accomplished with a counter (2K SubCnt) performing operations overtwo, instead of six or eight, cycles. In order to accomplish DDS, atotal of four cycles may be required. For instance, referring to the“Read” data, the dark signal R_(n−1) for row n−1 can be read duringclock period 1722; then all sub-pixels A_(n−1), B_(n−1), C_(n−1),D_(n−1) can be transferred to floating diffusion FD_(n−1) during clockperiod 1726 and the bright values A_(n−1), B_(n−1), C_(n−1), D_(n−1) canbe read during clock period 1728. Again DDS can be applied bysubtracting the dark values obtained during clock period 1722 from thebright values read during clock period 1728.

FIG. 18A illustrates a partial pixel timing readout scheme 1800 ofsignals corresponding to an HD mode using a global shutter sequenceaccording to an embodiment; and FIG. 18B illustrates a partial pixeltiming readout scheme 1850 of signals corresponding to the embodiment ofFIG. 18A. Unlike the timing readout scheme 1700, the readout schemes1800 and 1850 show timing for global shutter readout.

Again a counter with two cycles (2K SubCnt) is used to partition cycles1818-1840; however, instead of sequentially reading rows of binnedsub-pixels, all dark values are read, and then all bright values areread globally. For instance, during cycles 1818-1826 all dark values areread into memory. Then during cycles 1828-1832 all sub-pixels are binnedto transfer charge from each sub-pixel photodiode to its respective,shared floating diffusion. Next, all bright values which weretransferred to floating diffusions during cycles 1828-1832, are readduring cycles 1834-1840.

FIG. 19 illustrates a flowchart 1900 of dynamic pixel managementaccording to an embodiment. The flowchart 1900 includes an initialoperation step 1902, decision steps 1904, 1906, 1912, and mode operationsteps 1908, 1910, 1914, 1916, 1918. The initial operation step 1902 caninclude reading the desired camera format from a camera user. This stepcan include receiving input from a menu or external control panel.Following the initial operation step 1902, a DPM module or anotherprocessing element within a camera can perform the decision step 1904.Decision step 1904 determines if HD or UHD mode has been selected. If HDmode has been selected in decision step 1904, then DPM and/or a DPMmodule can control the CMOS image sensor to operate in HD mode withpixel binning, as indicated by the operation step 1910. Following step1910 the decision step 1912 determines if global shutter or rollingshutter is to be used. If global shutter mode has been selected indecision step 1912, then DPM and/or the DPM module can control the CMOSimage sensor to read pixels according to global shutter mode and pixelbinning with DDS noise reduction. If rolling shutter mode has beenselected in decision step 1912, then DPM and/or a DPM module can controlthe CMOS image sensor to read pixels according to rolling shutter modeand pixel binning with DDS noise reduction.

If UHD mode has been selected in decision step 1904, then the followingdecision step 1906 can determine if the CMOS image sensor is to becontrolled for dDDS or DDS noise cancellation. If the decision step 1906selects dDDS, then the DPM and/or the DPM module can control the CMOSimage sensor to operate in UHD mode with dDDS noise cancellation androlling shutter. If the decision step 1906 selects DDS, then the DPMand/or the DPM module can control the CMOS image sensor to operate inUHD mode with DDS noise cancellation and rolling shutter.

Although the DPM manages camera features described above include modesfor HD, UHD, rolling shutter, and global shutter, other configurationsare possible. Camera features can include, but are not limited to, depthof field, dynamic and static resolution, dynamic and static range,sensitivity and F-stop. For instance, the DPM can also be used toimplement camera F-stop features with at least 15 F-stops.

While aspects have been described in conjunction with the exampleimplementations outlined above, various alternatives, modifications,variations, improvements, and/or substantial equivalents, whether knownor that are or may be presently unforeseen, may become apparent to thosehaving at least ordinary skill in the art. Accordingly, the exampleimplementations of the invention, as set forth above, are intended to beillustrative, not limiting. Various changes may be made withoutdeparting from the spirit and scope of the aspects. Therefore, theaspects are intended to embrace all known or later-developedalternatives, modifications, variations, improvements, and/orsubstantial equivalents.

The previous description is provided to enable any person skilled in theart to fully understand the full scope of the disclosure. Modificationsto the various exemplary embodiments disclosed herein will be readilyapparent to those skilled in the art. Thus, the claims should not belimited to the various aspects of the disclosure described herein, butshall be accorded the full scope consistent with the language of claims.All structural and functional equivalents to the elements of the variousaspects described throughout this disclosure that are known or latercome to be known to those of ordinary skill in the art are expresslyincorporated herein by reference and are intended to be encompassed bythe claims. Moreover, nothing disclosed herein is intended to bededicated to the public regardless of whether such disclosure isexplicitly recited in the claims. No claim element is to be construedunder the provisions of 35 U.S.C. § 112(f), or analogous law injurisdictions other than the United States, unless the element isexpressly recited using the phrase “means for” or, in the case of amethod claim, the element is recited using the phrase “step for.”

What is claimed is:
 1. A_(n) image sensor, comprising: a plurality ofrows of pixels that each include at least one pixel having a pluralityof photodiodes and a common readout circuit configured to storerespective output voltages from each of the plurality of photodiodes;and an image sensor controller configured to concurrently control the atleast one pixel in at least two rows of the plurality of rows of pixels,such that respective output voltage of at least one photodiode in eachof the at least two rows of pixels is concurrently read out on at leastone readout channel coupled to the respective common readout circuits,wherein the at least two rows of pixels comprise a linear configurationand have a symmetrical layout that is identical to each other.
 2. Theimage sensor according to claim 1, wherein the at least one pixel ofeach row of pixels comprises a plurality of transfer gates that are eachcoupled to a corresponding photodiode of the plurality of photodiodes.3. The image sensor according to claim 2, wherein the common readoutcircuit is further configured to output the stored output voltage ofeach of the plurality of photodiodes to the at least one readoutchannel.
 4. The image sensor according to claim 2, wherein the imagesensor controller is further configured to sequentially activate eachtransfer gate of the plurality of transfer gates of the at least tworows of pixels to sequentially output respective output voltage of eachof the plurality of photodiodes in the respective pixel.
 5. The imagesensor according to claim 4, wherein the image sensor controller isfurther configured to concurrently activate each corresponding transfergate of the plurality of transfer gates in the at least two rows ofpixels, such that the output voltages from the respective photodiodes isconcurrently read out on the at least one readout channel as the imagesensor controller sequentially activates the respective transfer gatesin the at least two rows of pixels.
 6. The image sensor of claim 2,wherein a first photodiode of the plurality of photodiodes in the atleast one pixel in a first row of the at least two rows of pixels isassociated with a first transfer gate of the plurality of transfer gatesin the first row, and a first photodiode of the plurality of photodiodesin the at least one pixel in a second row of the at least two rows ofpixels is associated with a first transfer gate of the plurality oftransfer gates in the second row.
 7. The image sensor of claim 6,wherein the first photodiode in the at least one pixel in the first rowand the first photodiode in the at least one pixel in the second row areon different columns.
 8. The image sensor of claim 7, wherein a secondtransfer gate of the first plurality of transfer gates is coupled to asecond transfer gate of the second plurality of transfer gates.
 9. Theimage sensor of claim 8, further comprising: a third row of pixelscomprising a third pixel that includes: a plurality of photodiodes, aplurality of transfer gates coupled to the plurality of photodiodes ofthe third row of pixels, and a common readout circuit that includes acommon storage node physically positioned between each of the pluralityof photodiodes and the at least one readout channel and that isconfigured to store an output voltage from each of the plurality ofphotodiodes of the third row of pixels and output the stored outputvoltage to the at least one readout channel.
 10. The image sensor ofclaim 9, wherein one of the at least two rows of pixels is directlyadjacent to the third row of pixels.
 11. The image sensor of claim 2,wherein a connection for coupling respective transfer gates of the atleast two rows of pixels is at an edge of an image area including the atleast two rows of pixels.
 12. The image sensor of claim 1, wherein theat least two rows of pixels are directly adjacent to each other in ahorizontal layout of the image sensor.
 13. The image sensor of claim 1,further comprising a first operational mode controller configured tocontrol the image sensor in a first operational mode to concurrentlysample output values of respective plurality of photodiodes in at leastone row of the at least two rows of pixels.
 14. The image sensoraccording to claim 13, wherein the first operational mode is a highdefinition (HD) mode and a second operational mode is an ultra-highdefinition (UHD) mode.
 15. The image sensor according to claim 14,further comprising an image generating unit configured to generate imagedata based on at least one of the individually sampled photodiodesduring the UHD mode and the collectively sampled photodiodes during theHD mode.
 16. The image sensor according to claim 15, further comprisinga second operation mode controller configured to control the imagesensor to sequentially transfer charge between at least two photodiodesof the plurality of photodiodes of the at least one row of the at leasttwo rows of pixels and the respective common readout circuit
 17. Theimage sensor according to claim 16, wherein the second operation modecontroller is further configured to control the image sensor to samplephotodiode outputs according to a rolling shutter exposure sequenceduring the UHD mode.
 18. A_(n) image sensor controller for controlling apixel array having a plurality of rows of pixels that each have aplurality of photodiodes and a common readout circuit, the image sensorcontroller comprising: an image sensor controlling means forconcurrently controlling at least one pixel in at least two rows of theplurality of rows of pixels to concurrently generate respective outputvoltages from at least one photodiode in each of the at least two rowsof pixels, with the at least two rows of pixels having a linearconfiguration and a symmetrical layout that is identical to each other;and a readout controlling means for controlling the at least one pixelin the at least two rows of pixels to concurrently read out therespective output voltages on at least one readout channel coupled tothe respective common readout circuits.
 19. The image sensor controlleraccording to claim 18, further comprising means for controlling thecommon readout circuit to output the stored output voltage of each ofthe plurality of photodiodes to the at least one readout channel. 20.The image sensor controller according to claim 19, further comprisingmeans for sequentially activating each transfer gate of a plurality oftransfer gates in the at least two rows of pixels to sequentially outputrespective output voltage of each of the plurality of photodiodes in therespective pixel row.
 21. The image sensor controller according to claim20, further comprising transfer gate controlling means for concurrentlyactivating each corresponding transfer gate of the plurality of transfergates in the at least two rows of pixels, such that the output voltagesfrom the respective photodiodes is concurrently read out on the at leastone readout channel as the image sensor controller sequentiallyactivates the respective transfer gates in the at least two rows ofpixels.
 22. The image sensor controller of claim 20, further comprisingconnection means for coupling respective transfer gates of the at leasttwo rows of pixels is at an edge of an image area including the at leasttwo rows of pixels.
 23. The image sensor controller of claim 18, furthercomprising a first operational mode controller means for controlling theimage sensor in a first operational mode to concurrently sample outputvalues of respective plurality of photodiodes in at least one row of theat least two rows of pixels.
 24. The image sensor controller accordingto claim 23, wherein the first operational mode is a high definition(HD) mode and a second operational mode is an ultra-high definition(UHD) mode.
 25. The image sensor controller according to claim 24,further comprising an image generating means for generating image databased on at least one of the individually sampled photodiodes during theUHD mode and the collectively sampled photodiodes during the HD mode.26. The image sensor controller according to claim 22, furthercomprising a second operation mode controlling means for controlling theimage sensor to sequentially transfer charge between at least twophotodiodes of the plurality of photodiodes of the at least one row ofthe at least two rows of pixels and the respective common readoutcircuit
 27. The image sensor controller according to claim 26, whereinthe second operation mode controlling means controls the image sensor tosample photodiode outputs according to a rolling shutter exposuresequence during the UHD mode.
 28. A_(n) image sensor controller forperforming digital sampling of pixel values of an image sensor, theimage sensor controller comprising: means for reading out a first pixelvalue from a first pixel on a first pixel row by applying a first signalto the first pixel, the first pixel including a first plurality ofphotodiodes, and the first pixel value from the first pixel being readout from a first one of the photodiodes of the first plurality ofphotodiodes; and means for reading out a first pixel value from a secondpixel on a second pixel row by concurrently applying the first signal tothe second pixel that includes a second plurality of photodiodes, withthe first pixel value from the second pixel being read out from a firstone of the photodiodes of the second plurality of photodiodes, and thefirst and second pixel rows having a linear configuration and asymmetrical layout that is identical to each other.
 29. The image sensorcontroller of claim 28, wherein the first pixel row is adjacent to thesecond pixel row, and the first pixel is adjacent to the second pixel.30. The image sensor controller of claim 29, wherein the first one ofthe photodiodes of the first plurality of photodiodes and the first oneof the photodiodes of the second plurality of photodiodes are ondifferent columns.
 31. The image sensor controller of claim 29, whereinthe first pixel value from the first pixel is read out during a firstclock cycle, wherein the first pixel value from the second pixel is readout during a second clock cycle, and the first clock cycle and thesecond clock cycles are consecutive clock cycles.
 32. The image sensorcontroller of claim 28, further comprising: means for reading out asecond pixel value from the first pixel by applying a second signal tothe first pixel, the second pixel value from the first pixel being readout from a second one of the photodiodes of the first plurality ofphotodiodes; and means for reading out a second pixel value from thesecond pixel by concurrently applying the second signal to the secondpixel, the second pixel value from the second pixel being read out froma second one of the photodiodes of the second plurality of photodiodes.33. The image sensor controller of claim 32, wherein the second one ofthe photodiodes of the first plurality of photodiodes and the second oneof the photodiodes of the second plurality of photodiodes are ondifferent columns.
 34. The image sensor controller of claim 32, whereinthe second pixel value from the first pixel is read out during a firstclock cycle, and wherein the second pixel value from the second pixel isread out during a second clock cycle, and the first clock cycle and thesecond clock cycles being consecutive clock cycles.
 35. The image sensorcontroller according to claim 28, further comprising means forsequentially activating each transfer gate of a plurality of transfergates in the first and second pixel rows to sequentially outputrespective pixel values of each of the plurality of photodiodes in therespective pixel row.
 36. The image sensor controller according to claim35, further comprising means for concurrently activating eachcorresponding transfer gate of the plurality of transfer gates in thefirst and second pixel rows, such that the pixel values from therespective photodiodes is concurrently read out on at least one readoutchannel as the image sensor controller sequentially activates therespective transfer gates in the first and second pixel rows.
 37. Theimage sensor controller of claim 36, further comprising connection meansfor coupling respective transfer gates of the first and second pixelrows at an edge of an image area including the first and second pixelrows.